Impact of FPGA Technology Process on Depandability of Counters
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F11%3A00182617" target="_blank" >RIV/68407700:21240/11:00182617 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Impact of FPGA Technology Process on Depandability of Counters
Original language description
This paper discusses a technology and a structure of FPGAs. Our aim is to design dependable systems. Most of them are based on FPGAs, because of shorter time to market, easy designing of complex circuits and lower price in comparison to ASIC. Consequently our research is aimed to using FPGAs, in which the security is given by hardware organization and due to this is higher than on PC based devices.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the Work in Progress Session - DSD 2011
ISBN
978-3-902457-30-1
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
33-34
Publisher name
University of Oulu
Place of publication
Oulu
Event location
Oulu
Event date
Aug 31, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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