Optimization of the bond and etch-back silicon-on-insulator manufacturing processes

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F26821532%3A_____%2F13%3A%230000034" target="_blank" >RIV/26821532:_____/13:#0000034 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Optimization of the bond and etch-back silicon-on-insulator manufacturing processes
Original language description
We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 um thick SiGeB etch-stop layer, through 850C/12 h bond strengthening annealing and selective etching, to the ?nal chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydro?uoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 um, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1um. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0
Czech name
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Czech description
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Type
J<sub>x</sub> - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)
CEP classification
JJ - Other materials
OECD FORD branch
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Project
<a href="/en/project/TA01010078" target="_blank" >TA01010078: SOI Structures for Advanced Semiconductor Applications</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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