Built-In Self Test From Hardware Point of View
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F01%3A00000009" target="_blank" >RIV/46747885:24220/01:00000009 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
Built-In Self Test From Hardware Point of View
Original language description
In this paper we present experiences with BISTE (Built-In Self Test Equipment) from hardware point-of-view. Circuit scheme consists of the CUT (Circuit Under Test), TPG (Test Pattern Generator - part of the BIST which prepares test patterns and forces itAll these parts have an influence on the dimensions of the final IC. Different test techniques have different hardware overhead demands. We have done the comparison of the basic flip-flops (FF), which we have used for the TPG design. We also demonstratean influence of the used BISTE technique to the hardware overhead.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
—
Result continuities
Project
<a href="/en/project/GA102%2F01%2F0566" target="_blank" >GA102/01/0566: Built-in self test equipment optimisation methods in integrated circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2001
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
5th Workshop on Electronics, Control, Modelling, Measurment and Signals
ISBN
—
ISSN
—
e-ISSN
—
Number of pages
5
Pages from-to
131-135
Publisher name
Universite Paul Sabatier
Place of publication
Toulouse, France
Event location
Toulouse
Event date
May 30, 2001
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—