Hardware Overhead of Boundary Scan and RAS Design Methodologies
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F02%3A00000002" target="_blank" >RIV/46747885:24220/02:00000002 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Hardware Overhead of Boundary Scan and RAS Design Methodologies
Original language description
In this paper we present results of our experiments with integrated circuit BISTE. We have compared the hardware overhead of the BS diagnostic equipment with the RAS design. We have built the RAS diagnostic equipment with the same controlling circuitry aFurther area reduction can be obtained by using built-in TPG on chip. These generators spare the memory for storing the test vectors. We have found that when using this kind of test pattern generators the total area devoted for diagnostics is the lowest
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F01%2F0566" target="_blank" >GA102/01/0566: Built-in self test equipment optimisation methods in integrated circuits</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2002
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 5th International workshop IEEE DDECS2002
ISBN
80-214-2094-4
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
36-43
Publisher name
Brno University of Technology, faculty of Information Technology
Place of publication
Brno, Czech
Event location
Brno, Czech
Event date
Apr 17, 2002
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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