Hardware Overhead of BIST Equipment

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F01%3A00000010" target="_blank" >RIV/46747885:24220/01:00000010 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Hardware Overhead of BIST Equipment
Original language description
In this paper we present the results of our experiences with IC (integrated Circuit) BISTE (Built-In Self Test Equipment) from hardware point-of-view. The scheme of circuit consists in the CUT (Circuit Under Test), TPI (Test Pattern Input) and response evaluator. All these parts have a significant influence on the dimensions of the final chip area of the IC. Different test techniques have different hardware overhead demands. We have done the comparison of the basic flip-flops (FF), which we used for theTPG (Test Pattern Generator) design. We also demonstrate an influence of the used BISTE technique to the hardware overhead (the area of the whole IC which is occupied by BIST part of the circuit).
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F01%2F0566" target="_blank" >GA102/01/0566: Built-in self test equipment optimisation methods in integrated circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2001
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
International Conference Applied Electronics 2001
ISBN
80-7082-758-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
204-207
Publisher name
Západočeská Universita v Plzni
Place of publication
Plzeň
Event location
Plzeň
Event date
Sep 5, 2001
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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