Low power Boundary Scan Design

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F02%3A00000003" target="_blank" >RIV/46747885:24220/02:00000003 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Low power Boundary Scan Design
Original language description
In this paper we propose a low power modification of scan design methodology. In order to maximize power savings and minimize the hardware overhead we have proposed a modified BS diagnostic access method, which combines RAS and BS diagnostic access. Thismethod does not cause unwanted node transitions in the circuit during test patterns loading and the modified cells have lower power consumption than it is in the case of BS.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F01%2F0566" target="_blank" >GA102/01/0566: Built-in self test equipment optimisation methods in integrated circuits</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2002
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 8th Biennial Baltic Electronics Conference
ISBN
9985-59-292-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
265-268
Publisher name
dept. Of Electronics of Tallinn Technical University
Place of publication
Tallinn, Estonia
Event location
Tallinn, Estonia
Event date
Oct 6, 2002
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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