Test-Data Compression with Low Number of Channels and Short Test Time
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F14%3A%230003128" target="_blank" >RIV/46747885:24220/14:#0003128 - isvavai.cz</a>
Result on the web
<a href="http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=3&SID=R2Ihc8Vb4DCzHkD6jzl&page=1&doc=1" target="_blank" >http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=3&SID=R2Ihc8Vb4DCzHkD6jzl&page=1&doc=1</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Test-Data Compression with Low Number of Channels and Short Test Time
Original language description
The paper describes a modified Smart BIST methodology that provides test data volume compression. The test equipment is easily applicable because it is based on the standard scan methodology. The method is based on continuous LFSR reseeding decompressionthat is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. The parameters can be tuned in such a waythat the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS)
ISBN
978-1-4799-4558-0
ISSN
2334-3133
e-ISSN
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Number of pages
6
Pages from-to
104-109
Publisher name
IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Place of publication
Warsaw, POLAND
Event location
Warsaw, POLAND
Event date
Jan 1, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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