Test Pattern Decompression in Parallel Scan Chain Architecture
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F13%3A00215127" target="_blank" >RIV/68407700:21240/13:00215127 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DDECS.2013.6549820" target="_blank" >http://dx.doi.org/10.1109/DDECS.2013.6549820</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2013.6549820" target="_blank" >10.1109/DDECS.2013.6549820</a>
Alternative languages
Result language
angličtina
Original language name
Test Pattern Decompression in Parallel Scan Chain Architecture
Original language description
The paper presents a test-data volume-compression method which reduces test time and hardware overhead by test pattern broadcast into parallel scan chains. The proposed hardware enables efficient test pattern decompression and test response compaction. It uses a XOR-less structure instead of ring generators for test pattern decompression. Decompressed test vectors are obtained from the previously generated ones by simple shift operations only. The compression algorithm can search in a wider pattern space when finding the best fitting decompressor seed sequence because of this arrangement. The faults of basic gates can be covered by the patterns easily obtained in the decompressor during several clock cycles as a majority of faults can be tested by patterns that differ in a few shift operations only. The paper describes a test pattern decompressor hardware including its controller. The decompressor reduces the number of flip-flops containing information about previously generated patter
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
ISBN
978-1-4673-6135-4
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
219-223
Publisher name
IEEE
Place of publication
New York
Event location
Karlovy Vary
Event date
Apr 8, 2013
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
000325168900046