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On test time reduction using pattern overlapping, broadcasting and on-chip decompression

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F12%3A00195640" target="_blank" >RIV/68407700:21240/12:00195640 - isvavai.cz</a>

  • Result on the web

    <a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6219078&isnumber=6219000" target="_blank" >http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6219078&isnumber=6219000</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DDECS.2012.6219078" target="_blank" >10.1109/DDECS.2012.6219078</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    On test time reduction using pattern overlapping, broadcasting and on-chip decompression

  • Original language description

    The paper deals with the problem of test data volume, test application time and on-chip test decompressor hardware overhead of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements. This paper presents a new test compression and test application approach that combines boththe test pattern overlapping technique and the test pattern broadcasting technique. This new technique significantly reduces test application time by utilizing a new on-chip test decompressor architecture presented in this paper.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2012

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

  • ISBN

    978-1-4673-1185-4

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    300-305

  • Publisher name

    IEEE Computer Society Press

  • Place of publication

    New York

  • Event location

    Tallinn

  • Event date

    Apr 18, 2012

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article