Test compression for circuits with multiple scan chains

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F15%3A%230003422" target="_blank" >RIV/46747885:24220/15:#0003422 - isvavai.cz</a>
Result on the web
<a href="http://www.scopus.com/record/display.uri?eid=2-s2.0-84933545367&origin=resultslist&sort=plf-f&src=s&st1=Test+Compression+for+Circuits+with+Multiple+Scan+Chains&st2=&sid=78DE9ACA07CFA6FF3C0DC1353B741796.y7ESLndDIsN8cE7qwvy6w%3a20&am" target="_blank" >http://www.scopus.com/record/display.uri?eid=2-s2.0-84933545367&origin=resultslist&sort=plf-f&src=s&st1=Test+Compression+for+Circuits+with+Multiple+Scan+Chains&st2=&sid=78DE9ACA07CFA6FF3C0DC1353B741796.y7ESLndDIsN8cE7qwvy6w%3a20&am</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/LATW.2015.7102510" target="_blank" >10.1109/LATW.2015.7102510</a>

Result language
angličtina
Original language name
Test compression for circuits with multiple scan chains
Original language description
The paper presents a test pattern compression method for circuits with a high number of parallel scan chains. It reduces test time while it keeps hardware overhead low. The decompression method is based on the continuous LFSR reseeding that is used in such a way that it enables LFSR lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. The paper discusses decompression effectiveness for different LFSR shapes,scan chain lengths and numbers of parallel LFSR inputs. We have found that it is hardware saving to use an LFSR with the state skipping instead of using a LFSR accompanied with a phase shifter. It can be designed in such a way that it uses a lower numberof internal XOR gates, guarantees maximum separation between scan chains and does not introduce an extra delay on the LFSR outputs. Experimental results on benchmark circuits have shown that the presented test pattern decompression provi
Czech name
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Czech description
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Project
<a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
16th IEEE Latin-American Test Symposium, LATS 2015
ISBN
978-1-4673-6710-3
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
"neuvedeno"
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Puerto Vallarta; Mexico
Event location
Puerto Vallarta; Mexico
Event date
Jan 1, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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