LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F15%3A%230003423" target="_blank" >RIV/46747885:24220/15:#0003423 - isvavai.cz</a>
Result on the web
<a href="http://www.scopus.com/record/display.uri?eid=2-s2.0-84954165404&origin=resultslist&sort=plf-f&src=s&st1=LFSR+Reseeding+Based+Test+Compression+Respecting+Different+Controllability+of+Decompressor+Outputs&st2=&sid=7A5990F34926095A86D" target="_blank" >http://www.scopus.com/record/display.uri?eid=2-s2.0-84954165404&origin=resultslist&sort=plf-f&src=s&st1=LFSR+Reseeding+Based+Test+Compression+Respecting+Different+Controllability+of+Decompressor+Outputs&st2=&sid=7A5990F34926095A86D</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2015.28" target="_blank" >10.1109/DDECS.2015.28</a>
Alternative languages
Result language
angličtina
Original language name
LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs
Original language description
The paper discusses possibilities of rearranging test decompress or internal structure and linking its outputs with the parallel scan chain inputs in order to obtain better compression efficiency while the hardware overhead is not increased. We have experimentally verified that the controllability of decompress or outputs can be used as a simple and easily computable measure of the decompress or efficiency. Based on this observation we have developed a procedure that chooses a sub optimal LFSR outputs and parallel scan chain inputs interconnection. The procedure proposes a permutation of the scan chain inputs so that the scan chains that are fed with patterns with higher number of care bits are linked with the highly controllable decompress or outputs.We have experimentally verified on the benchmark circuits that adopting the proposed strategy improves the compression efficiency.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/LD13019" target="_blank" >LD13019: Improvement in Reliability of Nano-scale circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
ISBN
978-1-4799-6780-3
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
9-14
Publisher name
Institute of Electrical and Electronics Engineers Inc.
Place of publication
Belgrade, Serbia
Event location
Belgrade, Serbia
Event date
Jan 1, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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