FPGA realization of the digital frequency synthesizer

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F03%3A00000027" target="_blank" >RIV/49777513:23220/03:00000027 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

FPGA realization of the digital frequency synthesizer

Original language description

This paper describes a new architecture of a digital frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other methods. Presented synthesizer is the most suitable for the design of VLSI architectures or for programmable logical devices (CPLD, FPGA). This synthesizer has a disadvantage in low output frequency, which can be overcome by using this synthesizer together with phase-locked loop.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

<a href="/en/project/LN00B084" target="_blank" >LN00B084: Research Centre for New Technologies in the Region of West Bohemia</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2003

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Applied Electronics 2003

ISBN

80-7082-951-6

ISSN

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e-ISSN

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Number of pages

3

Pages from-to

205-207

Publisher name

University of West Bohemia

Place of publication

Pilsen

Event location

ZČU FEL Plzeň

Event date

Sep 10, 2003

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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