Frequency Synthesizer Based on Flying Adder Architecture and Phase Locked Loop
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F11%3A43898434" target="_blank" >RIV/49777513:23220/11:43898434 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Frequency Synthesizer Based on Flying Adder Architecture and Phase Locked Loop
Original language description
Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is based on a new concept time-average-frequency, to generate frequencies. This paper presents fractional frequencysynthesizer architecture based on concept flying-adder and phase locked loop principle. The simulation results concerning this system are presented.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
MEASUREMENT
ISBN
978-80-969672-4-7
ISSN
0263-2241
e-ISSN
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Number of pages
4
Pages from-to
278-281
Publisher name
Slovak Academy of Sciences
Place of publication
Bratislava
Event location
Slovensko, Smolenice
Event date
Apr 27, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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