Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F14%3A43921954" target="_blank" >RIV/49777513:23220/14:43921954 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6868819" target="_blank" >http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6868819</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2014.6868819" target="_blank" >10.1109/DDECS.2014.6868819</a>
Alternative languages
Result language
angličtina
Original language name
Efficient VHDL Implementation of Symbol Synchronization for Software Radio based on FPGA
Original language description
The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of digital receiver is symbol synchronization block. The goal of this paper is to develop efficient Non-Data-Aided (NDA) feedback PLL-based synchronization scheme in VHDL language for RTL synthesis on FPGA. The first part of this paper is focused on formulation Maximum Likelihood (ML) criterion for timing error detector. This approach forms basic assumptions for derivation of the other timing error detectors like Zero-Crossing detector. The extensive emphasis will be put on simulation of synchronization models. This model is composed of interpolating filter, error timing detector and interpolation control block. The second part of this paper deals with simulation of proposed fully pipelined VHDL model and the results of RTL synthesis are discussed.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
ISBN
978-1-4799-4558-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
318-321
Publisher name
IEEE (The Institute of Electrical and Electronics Engineers)
Place of publication
Varšava
Event location
Varšava
Event date
Apr 23, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000346734200069