All

What are you looking for?

All
Projects
Results
Organizations

Quick search

  • Projects supported by TA ČR
  • Excellent projects
  • Projects with the highest public support
  • Current projects

Smart search

  • That is how I find a specific +word
  • That is how I leave the -word out of the results
  • “That is how I can find the whole phrase”

Symbol synchronization for SDR using a polyphase filterbank based on an FPGA

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F15%3A43925770" target="_blank" >RIV/49777513:23220/15:43925770 - isvavai.cz</a>

  • Result on the web

    <a href="http://www.radioeng.cz/fulltexts/2015/15_03_0772_0782.pdf" target="_blank" >http://www.radioeng.cz/fulltexts/2015/15_03_0772_0782.pdf</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.13164/re.2015.0772" target="_blank" >10.13164/re.2015.0772</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Symbol synchronization for SDR using a polyphase filterbank based on an FPGA

  • Original language description

    This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource util

  • Czech name

  • Czech description

Classification

  • Type

    J<sub>x</sub> - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

  • CEP classification

    JA - Electronics and optoelectronics

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2015

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Name of the periodical

    Radioengineering

  • ISSN

    1210-2512

  • e-ISSN

  • Volume of the periodical

    24

  • Issue of the periodical within the volume

    3

  • Country of publishing house

    CZ - CZECH REPUBLIC

  • Number of pages

    11

  • Pages from-to

    772-782

  • UT code for WoS article

    000362304000016

  • EID of the result in the Scopus database