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High efficient carrier phase synchronization for SDR using CORDIC implemented on an FPGA

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F15%3A43927133" target="_blank" >RIV/49777513:23220/15:43927133 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    High efficient carrier phase synchronization for SDR using CORDIC implemented on an FPGA

  • Original language description

    This paper is devoted to the proposal of a highly efficient carrier phase synchronization subsystem for Software Defined Receiver. The proposed feedback phaselocked loop carrier synchronizer is suitable for parallel implementation on an FPGA for QPSK with the possibility of extension for m-QAM modulation. Direct Digital Synthesizer uses CORDIC algorithm in rotation mode for calculation of the sine and cosine of an angle. The angle of rotation is the uncompensated carrier phase offset. The carrier phaseoffset is derived by the closed-loop path created by phase error detector, PLL loop filter and accumulator control block. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete,fully pipelined VHDL description model is created. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JA - Electronics and optoelectronics

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/ED2.1.00%2F03.0094" target="_blank" >ED2.1.00/03.0094: Regional Innovation Centre for Electrical Engineering (RICE)</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2015

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of Papers : 2015 23rd Telecommunications Forum (TELFOR 2015)

  • ISBN

    978-1-5090-0055-5

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    512-515

  • Publisher name

    IEEE

  • Place of publication

    Piscataway

  • Event location

    Bělehrad, Srbsko

  • Event date

    Nov 24, 2015

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article