High performance VHDL FIR filter structure for symbol timing system implemented on FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F14%3A43923596" target="_blank" >RIV/49777513:23220/14:43923596 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
High performance VHDL FIR filter structure for symbol timing system implemented on FPGA
Original language description
The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. Digital filters are necessary in transmitter / receiver side and FIR filters are often chosen for their beneficial properties against IIR filters. Symbol synchronization subsystem also maintains digital filters for interpolation purpose. The goal of this paper is to develop efficient fully parallel FIR filter structure in VHDL language for symbol synchronization purpose. The first part of this paper is focused on formulation distributed arithmetic technique for proposed FIR filter. The second part describes incorporation of this filter to symbol synchronization subsystem. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size. The result of RTL synthesis on FPGA is finally discussed.
Czech name
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Czech description
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Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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