A scalable and low-power FPGA-aware network-on-chip architecture
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27740%2F18%3A10240673" target="_blank" >RIV/61989100:27740/18:10240673 - isvavai.cz</a>
Result on the web
<a href="https://link.springer.com/chapter/10.1007%2F978-3-319-61566-0_37" target="_blank" >https://link.springer.com/chapter/10.1007%2F978-3-319-61566-0_37</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/978-3-319-61566-0_37" target="_blank" >10.1007/978-3-319-61566-0_37</a>
Alternative languages
Result language
angličtina
Original language name
A scalable and low-power FPGA-aware network-on-chip architecture
Original language description
The growing demand for high-performance capabilities in data centers (DCs) leads to adopt heterogeneous solutions. The advantage of specialised hardware is a better support for different types of workloads, and a reduction of the power consumption. Among the others, FPGAs offer the unique capability to provide hardware specialisation and low power consumption. In this context, large arrays of simple and reconfigurable processing elements (PEs), known as coarse-grain reconfigurable arrays (CGRAs), represent a flexible solution for supporting heterogeneous workloads through a specialised instruction set that provides high performance in specific application domains (e.g., image recognition, patterns classification). However, efficient and scalable interconnections are required to sustain throughput and performance of CGRAs. To this end, networks-on-chip (NoCs) have been recognised as a viable solution for better data packet communication. In this paper, we propose an FPGA-aware NoC design targeting CGRAs with 128+ PEs. The proposed design leverages on a two-level topology to scale well with the increasing number of PEs, while the introduction of a software-defined reconfiguration capability offers the opportunity to tailor the set of resources assigned to a specific application. Partitions of physical resources (i.e., virtual domains) are built over the physical topology to meet the required performance, as well as to ease sharing physical chip resources among applications. Experimental evaluation shows the efficiency of our solution regarding used FPGA resources and power consumption.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Advances in Intelligent Systems and Computing. Volume 611
ISBN
978-3-319-61565-3
ISSN
2194-5357
e-ISSN
2194-5365
Number of pages
14
Pages from-to
407-420
Publisher name
Springer
Place of publication
Cham
Event location
Turín
Event date
Jul 10, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000432998800037