Next Generation of Architecture for Precise Time Measurements

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F15%3A10130523" target="_blank" >RIV/63839172:_____/15:10130523 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/EWDTS.2015.7493161" target="_blank" >http://dx.doi.org/10.1109/EWDTS.2015.7493161</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/EWDTS.2015.7493161" target="_blank" >10.1109/EWDTS.2015.7493161</a>

Result language

angličtina

Original language name

Next Generation of Architecture for Precise Time Measurements

Original language description

This paper deals with a new generation of our adapters for atomic clock timescale comparison and other time measurements. Our currently operated adapters are based on Virtex 5 FPGA and the further development on this platform is obsolete. We describe our experience with FPGA based time measurement system consisting of one or two channel interpolating counter. We propose the new design based on the Zynq All Programmable SoC platform and present testing results.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

—

Project

<a href="/en/project/LM2010005" target="_blank" >LM2010005: Large Infrastructure CESNET</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2015

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

IEEE EAST-WEST DESIGN &amp; TEST SYMPOSIUM 2015

ISBN

978-1-4673-7776-8

ISSN

—

e-ISSN

—

Number of pages

3

Pages from-to

1-3

Publisher name

IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA

Place of publication

Batumi

Event location

Batumi, Gruzie

Event date

Sep 26, 2015

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000382527700052