Next generation of architecture for precise time measurements
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00300887" target="_blank" >RIV/68407700:21240/15:00300887 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/EWDTS.2015.7493161" target="_blank" >http://dx.doi.org/10.1109/EWDTS.2015.7493161</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/EWDTS.2015.7493161" target="_blank" >10.1109/EWDTS.2015.7493161</a>
Alternative languages
Result language
angličtina
Original language name
Next generation of architecture for precise time measurements
Original language description
This paper deals with a new generation of our adapters for atomic clock timescale comparison and other time measurements. Our currently operated adapters are based on Virtex 5 FPGA and the further development on this platform is obsolete. We describe our experience with FPGA based time measurement system consisting of one or two channel interpolating counter. We propose the new design based on the Zynq All Programmable SoC platform and present testing results.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of 2015 IEEE East-West Design & Test Symposium (EWDTS)
ISBN
978-1-4673-7775-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE
Place of publication
Piscataway
Event location
Batumi
Event date
Sep 26, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000382527700052