Live Demonstration of FPGA Based Networking Accelerator for 200 Gbps Data Transfers

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133020" target="_blank" >RIV/63839172:_____/18:10133020 - isvavai.cz</a>

Result on the web

<a href="https://www.liberouter.org/wp-content/uploads/2018/05/demo.pdf" target="_blank" >https://www.liberouter.org/wp-content/uploads/2018/05/demo.pdf</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/NOMS.2018.8406115" target="_blank" >10.1109/NOMS.2018.8406115</a>

Result language

angličtina

Original language name

Live Demonstration of FPGA Based Networking Accelerator for 200 Gbps Data Transfers

Original language description

CESNET (Czech NREN) is ready to demonstrate a new NFB-200G2QL accelerator with Virtex UltraScale+ FPGA specifically designed to push the achievable traffic processing throughput to 200 Gbps in a single card. Unique high-speed DMA engines in the FPGA together with highly optimized Linux drivers enable to achieve 200 Gbps data transfer through two PCIe Gen3 x16 interfaces with minimal CPU overhead. Captured network traffic can be independently distributed among individual cores of two physical CPUs (NUMA nodes) without utilization of QPI. As a result, wire-speed packet capture to the host memory from two fully saturated 100 Gbps Ethernet interfaces (QSFP28+) is achieved and various network monitoring applications can utilize the power of the latest FPGAs and CPUs for data processing. This is especially useful when traffic of both directions of a single 100GbE link needs to be processed. The proposed demonstration will show how the packets can be received from two 100 Gbps Ethernet links at full speed and captured to the host memory at 200 Gbps without any loss. The opposite direction of communication will also be shown, i.e. how the packets can be transmitted from the host memory towards the two 100GbE network interfaces. Achieved speeds will be demonstrated by counters and graphs showing generated, received/transmitted and captured packets. We will also show detailed statistics of CPU load during the packet capture/transmission for different packet lengths.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

IEEE/IFIP Network Operations and Management Symposium

ISBN

978-1-5386-3416-5

ISSN

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e-ISSN

neuvedeno

Number of pages

3

Pages from-to

1-3

Publisher name

IEEE

Place of publication

Neuveden

Event location

Taipei, Taiwan

Event date

Apr 23, 2018

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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