Demonstration of Full-Duplex Packet Transfers over PCI Express with Sustained 200 Gbps Throughput

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133090" target="_blank" >RIV/63839172:_____/18:10133090 - isvavai.cz</a>

Result on the web

<a href="https://www.liberouter.org/wp-content/uploads/2018/12/3optFA5vcJq2MkBSpUYVft.pdf" target="_blank" >https://www.liberouter.org/wp-content/uploads/2018/12/3optFA5vcJq2MkBSpUYVft.pdf</a>

DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Demonstration of Full-Duplex Packet Transfers over PCI Express with Sustained 200 Gbps Throughput

Original language description

CESNET (Czech NREN) and Netcope Technologies have a long research history in the area of high-speed network monitoring using FPGA accelerated cards (i.e. SmartNICs). Now, we are ready to demonstrate a new NFB-200G2QL accelerator specifically designed to push the achievable traffic processing throughput to 200 Gbps in a single card. The card is equipped with two 100 Gbps Ethernet interfaces (QSFP28+ standard), powerful Virtex UltraScale+ FPGA, and two PCIe Gen3 x16 interfaces. Unique high-speed DMA engines in the FPGA together with highly optimized Linux drivers enable to achieve 200 Gbps data transfer throughput through the PCIe interfaces with minimal CPU overhead. Captured network traffic can be independently distributed among individual cores of two physical CPUs (NUMA nodes) without utilization of QPI. As a result, wire-speed packet capture to the host memory from both fully saturated 100 Gbps Ethernet interfaces is achieved and various network monitoring applications can utilize the power of the latest FPGAs and CPUs for data processing. This is especially useful when traffic of both directions of a single 100GbE link needs to be processed. The proposed demonstration shows how packets of arbitrary length can be received from two 100 Gbps Ethernet links at wire-speed and captured to the host memory at sustained 200 Gbps without any loss. The opposite direction of communication is also shown, i.e. how packets can be transmitted from the host memory and fully saturate two 100 Gbps Ethernet network interfaces. The reception and the transmission of data can be even shown operating simultaneously (full-duplex) without any degradation of performance in either direction. Achieved throughputs are demonstrated by counters and graphs showing live statistics of generated, received/transmitted and captured packets. We can also show detailed statistics of CPU load during the transfers of data for different packet lengths.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT 2018)

ISBN

978-1-72810-214-6

ISSN

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e-ISSN

neuvedeno

Number of pages

4

Pages from-to

384-387

Publisher name

IEEE Computer Society Conference Publishing Services

Place of publication

Neuveden

Event location

Naha, Okinawa, Japan

Event date

Dec 10, 2018

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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