Accelerated Wire-Speed Packet Capture at 200 Gbps

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133029" target="_blank" >RIV/63839172:_____/18:10133029 - isvavai.cz</a>

Result on the web

<a href="http://kalman.mee.tcd.ie/fpl2018/content/pdfs/FPL2018-43iDzVTplcpussvbfIaaHz/1RK4kKR2T0tO90i0MlwR15/4AdLHCTNeGTcJTnyPTUal5.pdf" target="_blank" >http://kalman.mee.tcd.ie/fpl2018/content/pdfs/FPL2018-43iDzVTplcpussvbfIaaHz/1RK4kKR2T0tO90i0MlwR15/4AdLHCTNeGTcJTnyPTUal5.pdf</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/FPL.2018.00087" target="_blank" >10.1109/FPL.2018.00087</a>

Result language

angličtina

Original language name

Accelerated Wire-Speed Packet Capture at 200 Gbps

Original language description

We present our latest FPGA acceleration card NFB-200G2QL that is specifically designed to enable traffic processing at 200 Gbps. Unique high-speed DMA engines in the FPGA together with highly optimized Linux drivers enable data transfer through PCIe interfaces with minimal CPU overhead. Captured traffic can be independently distributed between individual cores of two physical CPUs (NUMA nodes) without utilization of QPI. As a result, wire-speed packet capture to the host memory from two fully saturated 100 Gbps Ethernet interfaces (QSFP28+ cages) is achieved and various network monitoring applications can utilize the power of the latest FPGAs and CPUs for data processing. This is especially useful when both directions of a single 100GbE link are monitored. The live demonstration shows how the packets are received from two 100 Gbps Ethernet links at wire-speed and captured to the host memory at 200 Gbps without a loss. The opposite direction of communication is also shown, i.e. how the packets are transmitted from the host memory and fully saturate the two 100GbE network interfaces. Achieved speeds are demonstrated by counters and gauges showing generated, received/transmitted and captured packets. We also show statistics of CPU load during the packet capture/transmission for different packet lengths.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

28th International Conference on Field Programmable Logic and Applications

ISBN

978-1-5386-8517-4

ISSN

1946-1488

e-ISSN

neuvedeno

Number of pages

2

Pages from-to

455-456

Publisher name

IEEE

Place of publication

Neuveden

Event location

Dublin, Ireland

Event date

Aug 26, 2018

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000460538500080