Verification of Generated RTL from P4 Source Code
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133074" target="_blank" >RIV/63839172:_____/18:10133074 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8526853&isnumber=8526788" target="_blank" >https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8526853&isnumber=8526788</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ICNP.2018.00065" target="_blank" >10.1109/ICNP.2018.00065</a>
Alternative languages
Result language
angličtina
Original language name
Verification of Generated RTL from P4 Source Code
Original language description
The P4 is a general and platform agnostic language for the description of packet processing functionality. So far it is being supported by a number of technology companies which provided a way for programming of their devices using the P4 language. One of possible platforms is a SmartNIC - a Field Programmable Gate Array (FPGA) device which connects flexibility with high performance into a compact package. FPGA circuits are typically programmed in a Hardware Description Language (HDL) like VHDL or Verilog. These languages are hard to learn for novices and the development of a network device is very time consuming. Therefore, researchers around the world are finding a way how to automate the translation process from P4 to HDL language because such approach allows easy and fast programming of FPGA SmartNICs to a big audience of network experts. There are currently available three main compilers for the translation of P4 source to HDL - SDNet P4FPGA and P4-to-VHDL. In our best knowledge, all mentioned compilers don't provide any automated test environment which can be used repeatedly for different P4 programs. In other words, the verification environment has to be written by hand for each P4 program. Our work demonstrates a possible solution for automated verification of generated Register Transfer Level (RTL) description of a packet processing device from provided P4 source code.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/TH02010214" target="_blank" >TH02010214: Platform for Acceleration of Network Functions Virtualization</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2018 IEEE 26th International Conference on Network Protocols
ISBN
978-1-5386-6043-0
ISSN
1092-1648
e-ISSN
neuvedeno
Number of pages
2
Pages from-to
444-445
Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Cambridge, Anglie
Event date
Sep 25, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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