High-Speed Computation of CRC Codes for FPGAs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133089" target="_blank" >RIV/63839172:_____/18:10133089 - isvavai.cz</a>
Alternative codes found
RIV/00216305:26230/18:PU130809
Result on the web
<a href="https://www.liberouter.org/wp-content/uploads/2018/12/1h3apS3aB66xEoBCc6mjCK.pdf" target="_blank" >https://www.liberouter.org/wp-content/uploads/2018/12/1h3apS3aB66xEoBCc6mjCK.pdf</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
High-Speed Computation of CRC Codes for FPGAs
Original language description
As the throughput of networks and memory interfaces is on a constant rise, there is a need for ever-faster error-detecting codes. Cyclic redundancy checks (CRC) are a common and widely used to ensure consistency or detect accidental changes of data. We propose a novel FPGA architecture for the computation of the CRC designed for general high-speed data transfers. Its key feature is allowing a processing of multiple independent data packets (transactions) in each clock cycle, what is a necessity for achieving high overall throughput on very wide data buses. Experimental results confirm that the proposed architecture reaches an effective throughput sufficient for utilization in multi-terabit Ethernet networks (over 2 Tbps or over 3000 Mpps) on a single Xilinx UltraScale+ FPGA.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT 2018)
ISBN
978-1-72810-214-6
ISSN
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e-ISSN
neuvedeno
Number of pages
4
Pages from-to
237-240
Publisher name
IEEE Computer Society Conference Publishing Services
Place of publication
Neuveden
Event location
Naha, Okinawa, Japan
Event date
Dec 10, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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