Effective FPGA Architecture for General CRC
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F19%3A10133159" target="_blank" >RIV/63839172:_____/19:10133159 - isvavai.cz</a>
Alternative codes found
RIV/00216305:26230/19:PU132249
Result on the web
<a href="http://dx.doi.org/10.1007/978-3-030-18656-2_16" target="_blank" >http://dx.doi.org/10.1007/978-3-030-18656-2_16</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/978-3-030-18656-2_16" target="_blank" >10.1007/978-3-030-18656-2_16</a>
Alternative languages
Result language
angličtina
Original language name
Effective FPGA Architecture for General CRC
Original language description
As throughputs of digital networks and memory interfaces are on a constant rise, there is a need for ever-faster implementations of error-detecting codes. Cyclic redundancy checks (CRC) are a common and widely used type of codes to ensure consistency or detect accidental changes of transferred data. We propose a novel FPGA architecture for the computation of the CRC values designed for general high-speed data transfers. Its key feature is allowing a processing of multiple independent data packets (transactions) in each clock cycle, what is a necessity for achieving high overall throughput on very wide data buses. The proposed approach can be effectively used in Ethernet MACs for different speeds, in Hybrid Memory Cube (HMC) controller, and in many other technologies utilizing any kind of CRC. Experimental results confirm that the proposed architecture enables reaching an effective throughput sufficient for utilization in multi-terabit Ethernet networks (over 2 Tbps or over 3000 Mpps) on a single Xilinx UltraScale+ FPGA. Furthermore, a better utilization of FPGA resources is achieved compared to existing CRC implementation for HMC controller (up to 70 % savings).
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings
ISBN
978-3-030-18655-5
ISSN
0302-9743
e-ISSN
—
Number of pages
13
Pages from-to
211-223
Publisher name
Springer International Publishing
Place of publication
Neuveden
Event location
Copenhagen, Denmark
Event date
May 20, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000489754600016