Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F20%3A10133291" target="_blank" >RIV/63839172:_____/20:10133291 - isvavai.cz</a>
Alternative codes found
RIV/00216305:26230/20:PU138631
Result on the web
<a href="http://dx.doi.org/10.1109/DSD51259.2020.00020" target="_blank" >http://dx.doi.org/10.1109/DSD51259.2020.00020</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD51259.2020.00020" target="_blank" >10.1109/DSD51259.2020.00020</a>
Alternative languages
Result language
angličtina
Original language name
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs
Original language description
As the throughput of computer networks and other peripheral interfaces is rising, developers are forced to use ever-wider data buses in FPGA designs. However, utilization of wide buses poses a serious threat of performance degradation, especially for the shortest data transactions (packets), as aliasing and alignment overheads on the bus can be extremely increased. In this paper, we propose a novel design method for the description of very wide data buses that we call Multi Buses.The key idea is to enable the processing of multiple transactions per clock cycle with very high and predictable effective throughput even in the worst-case. The feasibility of the proposed method is shown via analysis of achievable performance by both theoretical means and selected proof of concept implementations. Thanks to the proposed method, we were able to design FPGA cores for key operations in networking (e.g. parser, match table, CRC, deparser) with sufficient throughputs for wire-speed packet processing of 400 Gbps, 1 Tbps and even 2 Tbps Ethernet links.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 23rd Euromicro Conference on Digital Systems Design (DSD)
ISBN
978-1-72819-535-3
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
49-56
Publisher name
IEEE Computer Society
Place of publication
Neuveden
Event location
Kranj, Slovenia
Event date
Aug 26, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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