General memory efficient packet matching FPGA architecture for future high-speed networks

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU134971" target="_blank" >RIV/00216305:26230/20:PU134971 - isvavai.cz</a>

Alternative codes found

RIV/63839172:_____/20:10133221

Result on the web

<a href="http://www.sciencedirect.com/science/article/pii/S0141933119301334" target="_blank" >http://www.sciencedirect.com/science/article/pii/S0141933119301334</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.micpro.2019.102950" target="_blank" >10.1016/j.micpro.2019.102950</a>

Result language

angličtina

Original language name

General memory efficient packet matching FPGA architecture for future high-speed networks

Original language description

Packet classification (matching) is one of the critical operations in networking widely used in many different devices and tasks ranging from switching or routing to a variety of monitoring and security applications like firewall or IDS. To satisfy the ever-growing performance demands of current and future high-speed networks, specially designed hardware accelerated architectures implementing packet classification are necessary. These demands are now growing to such an extent, that in order to keep up with the rising throughputs of network links, the FPGA accelerated architectures are required to perform matching of multiple packets in every single clock cycle. To meet this requirement a simple replication approach can be utilized - instantiate multiple copies of a processing pipeline matching incoming packets in parallel. However, simple replication of pipelines inseparably brings a significant increase in utilization of FPGA resources of all types, which is especially costly for rather scarce on-chip memories used in matching tables. We propose and examine a unique parallel hardware architecture for hash-based exact match classification of multiple packets in each clock cycle that offers a reduction of memory replication requirements. The core idea of the proposed architecture is to exploit the basic memory organization structure present in all modern FPGAs, where hundreds of individual block or distributed memory tiles are available and can be accessed (addressed) independently. This way, we are able to maintain a rather high throughput of matching multiple packets per clock cycle even without fully replicated memory resources in matching tables. Our results show that the designed approach can use on-chip memory resources very efficiently and even scales exceptionally well with increased capacities of match tables. For example, the proposed architecture is able to achieve a throughput of more than 2 Tbps (over 3 000 Mpps) with an effec

Czech name

—

Czech description

—

Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2020

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

1872-9436

Volume of the periodical

73

Issue of the periodical within the volume

3

Country of publishing house

NL - THE KINGDOM OF THE NETHERLANDS

Number of pages

12

Pages from-to

1-12

UT code for WoS article

000520940000027

EID of the result in the Scopus database

2-s2.0-85076785576