Memory Aware Packet Matching Architecture for High-Speed Networks

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F18%3A10133027" target="_blank" >RIV/63839172:_____/18:10133027 - isvavai.cz</a>

Alternative codes found

RIV/00216305:26230/18:PU130782

Result on the web

<a href="http://dx.doi.org/10.1109/DSD.2018.00017" target="_blank" >http://dx.doi.org/10.1109/DSD.2018.00017</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2018.00017" target="_blank" >10.1109/DSD.2018.00017</a>

Result language

angličtina

Original language name

Memory Aware Packet Matching Architecture for High-Speed Networks

Original language description

Packet classification is a crucial operation for many different networking tasks ranging from switching or routing to monitoring and security devices like firewall or IDS. Generally, accelerated architectures implementing packet classification must be used to satisfy ever-growing demands of current high-speed networks. Furthermore, to keep up with the rising network throughputs, the accelerated architectures for FPGAs must be able to classify more than one packet in each clock cycle. This can be mainly achieved by utilization of multiple processing pipelines in parallel, what brings replication of FPGA logic and more importantly scarce on-chip memory resources. Therefore in this paper, we propose a novel parallel hardware architecture for hash-based exact match classification of multiple packets per clock cycle with reduced memory replication requirements. The basic idea is to leverage the fact that modern FPGAs offer hundreds of BlockRAM tiles that can be accessed (addressed) independently to maintain high throughput of matching even without fully replicated memory architecture. Our results show that the proposed approach can use memory very efficiently and scales exceptionally well with increased record capacities. For example, the designed architecture is able to achieve throughput of more than 2 Tbps (over 3 000 Mpps) with an effective capacity of more than 40 000 IPv4 flow records for the cost of only 366 BlockRAM tiles and around 57 000 LUTs.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of the 21st Euromicro Conference on Digital Systems Design

ISBN

978-1-5386-7376-8

ISSN

—

e-ISSN

neuvedeno

Number of pages

8

Pages from-to

1-8

Publisher name

IEEE Computer Society

Place of publication

Praha

Event location

Prague, Czech Republic

Event date

Aug 29, 2018

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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