Integrated iterative approach to FPGA placement.
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F03%3A16030183" target="_blank" >RIV/67985556:_____/03:16030183 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Integrated iterative approach to FPGA placement.
Original language description
This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use an unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Počítačové Architektury & Diagnostika PAD 2003.
ISBN
80-214-2471-0
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
43-50
Publisher name
VUT
Place of publication
Brno
Event location
Zvíkovské Podhradí [CZ]
Event date
Sep 24, 2003
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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