FPGA implementation of Finite Interval CMA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F05%3A00411312" target="_blank" >RIV/67985556:_____/05:00411312 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
FPGA implementation of Finite Interval CMA
Original language description
An FPGA implementation of the FI-CMA algorithm using the Virtex-E and Virtex-II devices is presented. The algorithm consists of two parts: one, performing batch-QR decomposition of the data matrix, and second, used for an iterative equalizer optimization, using the columns of the Q-matrix as input. The resource reuse and minimization of the total latency have been emphasized. Logarithmic arithmetic library has been used for floating point calculations, required in algorithm.
Czech name
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Czech description
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Project
<a href="/en/project/1ET300750402" target="_blank" >1ET300750402: Specification of quantitative criteria and optimalization of resources for broadband access networks</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the first annual IEEE BENELUX/DSP Valley Signal Processing Symposium. SPS-DARTS 2005
ISBN
0-7803-9333-3
ISSN
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e-ISSN
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Number of pages
3
Pages from-to
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Publisher name
IEEE
Place of publication
Antverpy
Event location
Antverpy
Event date
Apr 19, 2005
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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