Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F10%3A00346745" target="_blank" >RIV/67985556:_____/10:00346745 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
Original language description
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/7H09005" target="_blank" >7H09005: SCAlable LOw Power Embedded platformS</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the International Conference on Field Programmable Logic and Applications
ISBN
978-0-7695-4179-2
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE
Place of publication
Piscataway
Event location
Milano
Event date
Aug 31, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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