The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F11%3A00363078" target="_blank" >RIV/67985556:_____/11:00363078 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
Original language description
The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform.
Czech name
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Czech description
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Project
<a href="/en/project/7H10001" target="_blank" >7H10001: Smart Multicore Embedded SYstems</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing
ISBN
978-1-4577-0537-3
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
1657-1660
Publisher name
IEEE
Place of publication
Praha
Event location
Praha
Event date
May 22, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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