The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F67985556%3A_____%2F12%3A00376595" target="_blank" >RIV/67985556:_____/12:00376595 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor
Original language description
The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry outexperiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. We propose a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach firstconstructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. Our sample implementation that supports the Image Segmentation kernel is capable of 332 MFLOPs,400 MFLOPs, and 250 MFLOPs per coprocessor core in Virtex 5, Virtex 6 and Spartan 6 technologies, respectively. The core size is roughly 1500 slices, depending on the configuration and technology.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/7H10001" target="_blank" >7H10001: Smart Multicore Embedded SYstems</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4673-1185-4
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
62-67
Publisher name
IEEE
Place of publication
Tallinn, ESTONIA
Event location
Tallinn
Event date
Apr 18, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000312905700020