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Occurrence of Voids in Soldered Joints for Electrical Engineering

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21220%2F24%3A00378838" target="_blank" >RIV/68407700:21220/24:00378838 - isvavai.cz</a>

  • Alternative codes found

    RIV/68407700:21230/24:00378838

  • Result on the web

    <a href="https://doi.org/10.1109/ISSE61612.2024.10603930" target="_blank" >https://doi.org/10.1109/ISSE61612.2024.10603930</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/ISSE61612.2024.10603930" target="_blank" >10.1109/ISSE61612.2024.10603930</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Occurrence of Voids in Soldered Joints for Electrical Engineering

  • Original language description

    The research focuses on the occurrence of voids in soldered joints in the field of electrical engineering. The main goal was to analyze the occurrence of voids in soldered joints and to propose effective strategies to minimize this defect. BGA chips mounted on 10-layer PCBs were chosen as test samples. The current work focuses on defining production conditions and analyzing X-ray images. The analysis results implies that the parameters were chosen correctly and the acceptability criteria according to the ECSS-Q-ST-70-61C standard (defining soldering qualification for the space industry) were met with a margin, allowing for further types of tests such as vibration test and temperature cycling.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20201 - Electrical and electronic engineering

Result continuities

  • Project

  • Continuities

    I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Others

  • Publication year

    2024

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    2024 47th International Spring Seminar on Electronics Technology (ISSE)

  • ISBN

    979-8-3503-8548-9

  • ISSN

    2161-2536

  • e-ISSN

  • Number of pages

    5

  • Pages from-to

  • Publisher name

    IEEE Press

  • Place of publication

    New York

  • Event location

    Praha

  • Event date

    May 15, 2024

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    001283808200050