On-line Testing for FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F04%3A03099663" target="_blank" >RIV/68407700:21230/04:03099663 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
On-line Testing for FPGA
Original language description
This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed.
Czech name
Není k dispozici
Czech description
Není k dispozici
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2004
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004
ISBN
80-8073-150-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
194-199
Publisher name
Department of Computers and Informatics of FEI, Technical University Košice
Place of publication
Košice
Event location
Košice - Herľany
Event date
Sep 22, 2004
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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