Parity Codes Used for On-line Testing in FPGA

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03117292" target="_blank" >RIV/68407700:21230/05:03117292 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Parity Codes Used for On-line Testing in FPGA

Original language description

This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes.The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented.

Czech name

Parity Codes Used for On-line Testing in FPGA

Czech description

This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes.The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented.

Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2005

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Acta Polytechnica

ISSN

1210-2709

e-ISSN

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Volume of the periodical

45

Issue of the periodical within the volume

6

Country of publishing house

CZ - CZECH REPUBLIC

Number of pages

7

Pages from-to

53-59

UT code for WoS article

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EID of the result in the Scopus database

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