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Output Grouping-Based Decomposition of Logic Functions

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03108031" target="_blank" >RIV/68407700:21230/05:03108031 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Output Grouping-Based Decomposition of Logic Functions

  • Original language description

    We present a method allowing us to determine the grouping of the outputs of the multi output Boolean logic function for a single-level partitioning and minimization. Some kind of decomposition is often needed during the synthesis of logic circuits and the subsequent mapping onto technology. Sometimes a circuit has to be divided into several stand-alone parts, among its outputs, or possibly its inputs. It could be a case of a design targeted into PLAs, GALs, or any other monolithic components having a limited number of inputs and/or outputs. We propose a methodology to determine the way how the original circuit has to be partitioned into several parts of an arbitrary size, in order to reduce the complexity of the individual parts. The method is based onour FC-Min minimizer, even when no Boolean minimization has to be involved here. The efficiency of the method is demonstrated on the standard MCNC benchmarks.

  • Czech name

    Není k dispozici

  • Czech description

    Není k dispozici

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2005

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop

  • ISBN

    963 9364 48 7

  • ISSN

  • e-ISSN

  • Number of pages

    8

  • Pages from-to

    137-144

  • Publisher name

    University of Western Hungary

  • Place of publication

    Sopron

  • Event location

    Sopron

  • Event date

    Apr 13, 2005

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article