Fault Classification for Self-checking Circuits Implemented in FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03108032" target="_blank" >RIV/68407700:21230/05:03108032 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—

Result language
angličtina
Original language name
Fault Classification for Self-checking Circuits Implemented in FPGA
Original language description
This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups - the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on realbenchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered.
Czech name
Není k dispozici
Czech description
Není k dispozici

Project
<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
ISBN
963 9364 48 7
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
228-231
Publisher name
University of Western Hungary
Place of publication
Sopron
Event location
Sopron
Event date
Apr 13, 2005
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—

Similar results(10)