Multiple-Vector Column-Matching BIST Design Method

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A03120123" target="_blank" >RIV/68407700:21230/06:03120123 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Multiple-Vector Column-Matching BIST Design Method
Original language description
Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The column-matching algorithm is used to design the decoder. Using this algorithm, maximum of decoder outputs is tried to be matched with the decoder inputs, yielding the outputs be implemented as wires, thus without any logic. The newly proposed enhancement consistsin a major generalization of the method. The ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. The complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks.
Czech name
Není k dispozici
Czech description
Není k dispozici

Project
<a href="/en/project/GA102%2F04%2F2137" target="_blank" >GA102/04/2137: Design of highly reliable control systems built on dynamically reconfigurable FPGAs.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
ISBN
1-4244-0184-4
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
268-273
Publisher name
CTU Publishing House
Place of publication
Praha
Event location
Praha
Event date
Apr 18, 2006
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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