Column-matching based mixed-mode test pattern generator design technique for BIST

Result code in IS VaVaI

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Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Column-matching based mixed-mode test pattern generator design technique for BIST

Original language description

A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algorithm to synthesize the test pattern generator. In principle, we synthesize a combinational block - the Decoder,transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The Column Matching algorithm to design the decoder is proposed. Here the maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns, which reduces the BIST area overhead.

Czech name

Column-matching based mixed-mode test pattern generator design technique for BIST

Czech description

A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algorithm to synthesize the test pattern generator. In principle, we synthesize a combinational block - the Decoder,transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The Column Matching algorithm to design the decoder is proposed. Here the maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns, which reduces the BIST area overhead.

Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2008

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

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Volume of the periodical

32

Issue of the periodical within the volume

5-6

Country of publishing house

NL - THE KINGDOM OF THE NETHERLANDS

Number of pages

11

Pages from-to

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UT code for WoS article

000258992800013

EID of the result in the Scopus database

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