Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F08%3A00146273" target="_blank" >RIV/68407700:21230/08:00146273 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation
Original language description
This paper deals with the speed optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA). The presented scheduling algorithm use Integer Linear Programming (ILP) while complex algorithm structure is modeled by system of linear inequalities. The method is demonstrated on a LQ control algorithm. An advantage of the presented scheduling method is its suitability for algorithms with longer iteration period.
Czech name
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Czech description
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Classification
Type
O - Miscellaneous
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů