Optimization of Finite Interval CMA Implementation for FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A00111141" target="_blank" >RIV/68407700:21230/05:00111141 - isvavai.cz</a>
Alternative codes found
RIV/67985556:_____/05:00411508
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Optimization of Finite Interval CMA Implementation for FPGA
Original language description
The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using Integer Linear Programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization algorithm, with implementation using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. The approach is based on construction of an optimally scheduled abstract model, modeling imperfectly nested loops.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
IEEE 2005 Workshop on Signal Processing Systems (SIPS'05)
ISBN
0-7803-9333-3
ISSN
1520-6130
e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
IEEE
Place of publication
Piscataway
Event location
Athens
Event date
Nov 2, 2005
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000236758900014

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