Poly-phase Decimation Filter Implementation in VHDL
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F10%3A00170678" target="_blank" >RIV/68407700:21230/10:00170678 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Poly-phase Decimation Filter Implementation in VHDL
Original language description
In this article we describe our effort to create, model, implement and simulate a poly-phase decimation filter. It is to be used as a part of advanced radio transmission system. We describe the process of modeling the filter in Matlab in both floating and fixed point arithmetic for later implementation in VHDL language for FPGA. The complete system is then being simulated in ISim, compared with the model and results are presented and evaluated.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
RTT 2010 Proceedings
ISBN
978-80-248-2261-7
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
VŠB - TUO, FEI, Katedra elektroniky a telekomunikační techniky
Place of publication
Ostrava
Event location
Velké Losiny
Event date
Sep 8, 2010
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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