Digital Interpolator Implementation in VHDL

Result code in IS VaVaI
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Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Digital Interpolator Implementation in VHDL
Original language description
In this article we describe a creation, modeling, implementation and simulation of a digital interpolator. It will be used as a part of advanced radio transmission system. The input part of the system receiving part provides correct complex envelope sampling that is necessary for consequent signal processing. During the re-sampling, an interpolator co-operates with symbol timing estimator. It estimates correct sampling timing and controls an interpolator. We describe the process of interpolator modelingin Matlab in both floating and fixed point arithmetics for later implementation in the VHDL language for FPGA. The complete system was simulated in ISim, compared with the model and results are presented.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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