Novel Analog Synthesis Tool Implemented to the Cadence Design Environment
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F10%3A00173360" target="_blank" >RIV/68407700:21230/10:00173360 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Novel Analog Synthesis Tool Implemented to the Cadence Design Environment
Original language description
Analog synthesis is very hot topic at present. It can save enormous part of the design time. This paper presents work on novel analog synthesis tool capable of choosing circuit architecture and to size its devices by optimization to meet the design specification. This tool is implemented into Cadence design environment to be easily used by the analog designers.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1601" target="_blank" >GA102/09/1601: Intelligent micro and nano structures for microsensors realized with support of nanotechnology</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
The International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design 2010
ISBN
978-1-4244-6815-7
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
IEEE - Tunisia
Place of publication
Tunis
Event location
Gammarth
Event date
Oct 4, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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