A Co-Design Methodology for Processor-Centric Embedded Systems with Hardware Acceleration Using FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F12%3A00192387" target="_blank" >RIV/68407700:21230/12:00192387 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
A Co-Design Methodology for Processor-Centric Embedded Systems with Hardware Acceleration Using FPGA
Original language description
In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languagesand tools. The whole system is designed using well established high level modeling techniques, languages and tools from the software domain. That is, an OOP design approach expressed in UML and implemented in C++. Software coding effort is reduced sincethe C++ implementation not only provides a golden reference model, but may also be used as part of the final embedded software. Hardware coding effort is also reduced. The modular OOP design facilitates the engineer to ind the exact methods that need tobe accelerated by hardware using profiling tools, preventing useless translations to hardware. Moreover, the two-process structured VHDL design method used for hardware implementation has proven to reduce man-years, code lines and bugs i
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/MEB111009" target="_blank" >MEB111009: Cognitive learning autonomous robots for service</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 3th Southern Programmable Logic Conference
ISBN
978-1-4673-0185-5
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
7-14
Publisher name
IEEE
Place of publication
Piscataway
Event location
Bento Gonçalves
Event date
Mar 20, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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