An FPGA Algorithm Development for an Improved Servo-Loop Method

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F12%3A00195643" target="_blank" >RIV/68407700:21230/12:00195643 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
An FPGA Algorithm Development for an Improved Servo-Loop Method
Original language description
This paper deals with the FPGA (Field-Programmable Gate Array) implementation of the improved servo-loop algorithm, which has been already described in [1]. It is a new part of our testing environment for ADCs (Analog-to-Digital Converters). The articleis focused especially on the algorithm function and features. FPGA resources, measurement time consumption and recommended necessary improvements are also briefly discussed.
Czech name
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Czech description
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Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
ISBN
978-1-4673-1185-4
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
151-154
Publisher name
IEEE Computer Society Press
Place of publication
New York
Event location
Tallinn
Event date
Apr 18, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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