Lumped RF Model of MOSFET Gate Resistance for GHz+ Frequencies Enhancement of Compact BSIM MOSFET Model

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F15%3A00236413" target="_blank" >RIV/68407700:21230/15:00236413 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.15224/978-1-63248-077-4-22" target="_blank" >http://dx.doi.org/10.15224/978-1-63248-077-4-22</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.15224/978-1-63248-077-4-22" target="_blank" >10.15224/978-1-63248-077-4-22</a>

Result language
angličtina
Original language name
Lumped RF Model of MOSFET Gate Resistance for GHz+ Frequencies Enhancement of Compact BSIM MOSFET Model
Original language description
This paper presents a lumped RF model of high voltage FET applicable for the frequency up to GHz range. Unlike the compact MOSFET model, the proposed solution contains not only parasitic capacitances and resistances but also parasitic inductance. The signal delay caused by relatively large device area including the parasitic resonance modeled by distributed RLC network is considered. The model is applicable in commercial SPICE simulators, e.g. Eldo, Spectre or HSpice.
Czech name
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Czech description
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Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
The Third International Conference on Advances in Information Processing and Communication Technology - IPCT 2015
ISBN
978-1-63248-077-4
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
75-79
Publisher name
Institute of Research Engineers and Doctor
Place of publication
3905 State Street, Suite 7-31, Santa Barbara
Event location
Roma
Event date
Dec 10, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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