Techniques of JFET Gate Capacitance Modeling
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00305219" target="_blank" >RIV/68407700:21230/16:00305219 - isvavai.cz</a>
Result on the web
<a href="http://www.iaeng.org/publication/WCECS2016/WCECS2016_pp771-775.pdf" target="_blank" >http://www.iaeng.org/publication/WCECS2016/WCECS2016_pp771-775.pdf</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Techniques of JFET Gate Capacitance Modeling
Original language description
This paper presents various techniques and principles of modeling JFET gate capacitance. Various layout concepts as well as their gate capacitance measurements and modeling techniques are presented. Experience with potential modeling or measurement challenges is shared. The paper also deals with an often-omitted tight interaction between C-V and DC models, necessary for the well-fitting compact model. Good agreement has been achieved between measured silicon data and SPICE simulations for all discussed layout variants. Plots of various layouts and various tests from real production models are also presented.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
World Congress on Engineering and Computer Science 2016
ISBN
978-988-14048-2-4
ISSN
2078-0958
e-ISSN
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Number of pages
5
Pages from-to
771-775
Publisher name
Newswood Limited - International Association of Engineers
Place of publication
Hong Kong
Event location
San Francisco
Event date
Oct 19, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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